Efficient modelling of a PCB transmission line for high speed digital systems

dc.contributor.authorAcakpovi A.
dc.contributor.authorAsabere N.Y.
dc.contributor.authorSowah R.
dc.contributor.authorAbubakar R.
dc.contributor.authorAmo S.B.
dc.date.accessioned2025-03-06T18:11:43Z
dc.date.accessioned2025-03-06T18:59:08Z
dc.date.issued2018
dc.description.abstractThis paper proposes a model of PCB traces for high speed digital systems. The adopted approach involves predetermined geometry using direct discretization of transmission lines. Initially, the proposed methodology involves computing the line propagation delay by employing its geometry with associated empirical equations. The initial procedure paves the way to design a Lattice diagram which depicts multiple reflections that the signal underwent due to impedance mismatches between transmission lines and loads. Subsequent computations of electrical model parameters were further done. Simulation results using Multisim software illustrated a favorable performance with a time delay of 1.42 ns and an equivalent electrical model of 10 lumped LC cells. The time delay between input and output signal obtained from the simulation was approximately 15.152 ns corresponding to the time it took for a transmitted signal to reach a steady state which further signifies good performance of our proposed method. � 2018 IEEE.
dc.identifier.doi10.1109/ICASTECH.2018.8506779
dc.identifier.isbn978-153864233-7
dc.identifier.issn23269413
dc.identifier.urihttp://162.250.124.58:4000/handle/123456789/463
dc.language.isoen
dc.publisherIEEE Computer Society
dc.sourceIEEE International Conference on Adaptive Science and Technology, ICAST
dc.subjectDigital systems
dc.subjectLattice diagram
dc.subjectPCB traces
dc.subjectSignaling
dc.subjectTime delay
dc.subjectTransmission line modelling
dc.titleEfficient modelling of a PCB transmission line for high speed digital systems
dc.typeOther
oaire.citation.conferenceDate22 August 2018 through 24 August 2018
oaire.citation.conferencePlaceAccra

Files